Higher speed semiconductor devices may be attained by shrinking sizes and reducing parasitic capacitances. A typical Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) transistor is fabricated on a silicon substrate or within a well in the substrate, and has a large parasitic capacitance to this substrate or well.
However, the extremely tiny transistors have a thin gate oxide that can be damaged by relatively small currents with even a moderate driving force (voltage). Special care is required when a human handles these semiconductor devices.
Static electricity that normally builds up on a person can discharge across any pair of pins of a semiconductor integrated circuit (IC or chip). IC chips are routinely tested for resistance to such electrostatic discharges (ESD) using automated testers that apply a Human-Body Model (HBM) current pulse across different pairs of pins of the chip. Any pair of pins may be chosen for the ESD test.
More recently, planar MOSFET devices are being replaced by FinFET. FinFET uses a more three-dimensional transistor structure where the transistor gate is no longer within one single plane. FinFET uses a smaller area and tend to have smaller leakages than traditional planar transistors.
FIG. 1 shows a prior-art FinFET device. N+ regions 42, 44 are formed on the upper portion of the fin formed on substrate 20. The lower portion of the fin without N+ doping is surrounded by oxide 62. Substrate 20 can be a silicon substrate or an insulator for Silicon-On-Insulator (SOI) processes. N+ regions 42, 44 are very thin, having a slim, fin-like appearance. Between N+ region 42 and N+ region 44 is a connecting region of lightly-p-doped silicon that acts as the transistor channel. N+ region 42, the channel connecting region, and N+ region 44 can all be formed on the same fin of silicon.
Gate 52 is formed around the channel connecting region. Rather than being flat, gate 52 has an inverted U-shape that surrounds the channel connecting region between N+ regions 42, 44. Gate oxide 60 is formed on three sides of the fin-like channel connecting region rather than only on the top surface of the channel region.
FinFET transistors may have better current drive than equivalent flat transistors for the same die area due to this 3-D gate and channel structure. However, when a FinFET transistor is used for ESD protection, the high ESD currents can damage the FinFET transistor. In particular, extreme heating is sometimes seen in N+ region 42 near the junction to the channel region under gate 52. This extreme heating when a large ESD current passes through N+ region 42 can permanently damage gate oxide 60 and N+ region 42, causing the device to leak or malfunction.
Also, the thin or slim size of the fin used for N+ region 42 causes the current to be crowded into a narrow region, causing localized hot spots. Heat dissipation is hindered by the slim fin of N+ region 42 that is typically surrounded by an insulator including oxide 62 and a passivation insulator that covers everything, including N+ region 42, oxide 62, and gate 52.
FIG. 2 is a cross-section of the prior-art slim FinFET of FIG. 1. Slim fin 2 may be formed on substrate 20 to have a slim profile. Slim fin 2 is surrounded by oxide 62 which may form part of the gate oxide 60 between fin 2 and gate 52. A conducting channel is temporarily formed within slim fin 2 underneath gate 52 when a voltage is applied to gate 52 that is above the threshold voltage. This conducting channel allows current to flow from N+ region 42 to N+ region 44 through the p-type channel connecting region of slim fin 2 shown in FIG. 2.
During ESD testing, gate 52 is connected to ground for a Grounded-Gate NMOS device, so very little or no current is conducted through the p-type region of slim fin 2 that is not underneath gate 52 since no conducting channel is formed farther away from gate 52. However, when large ESD currents are applied, punch-through breakdown can occur where conduction may occur in the upper portion of slim fin 2, even farther below gate 52, not just in the conducting channel formed by the electric charge on gate 52.
FIG. 3 is an electrical schematic model of the FinFET of FIG. 2. The slim profile of the cross-section of slim fin 2 causes the gate conducting channel to have a relatively high resistance R2 between the source N+ region 42 and drain N+ region 44 (FIG. 1), when snap-back or punch-through breakdown occurs in the upper portion of slim fin 2.
One solution is to use a thicker profile for slim fin 2. A thicker or wider profile for slim fin 2 would allow for a larger ESD current to pass through, but the performance during normal operation might suffer since the fin under gate 52 would also be thicker. Thick fins could be used only for ESD devices, while more optimal thin fins are used for core transistors, but the process would be more complex and expensive since two different thicknesses of FinFET transistors are formed.
What is desired is a FinFET that is optimized for normal operation, yet is also designed to carry large ESD currents. A FinFET that can safely carry larger ESD currents while still using a slim fin for optimal transistor characteristics for normal operating currents is desirable. A hybrid FinFET transistor that is optimized for both regular operation and for ESD protection is desirable.